Nagim Ibragimov
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6-Bit ALU — Gate-Level VHDL & FPGA Implementation
FPGAVHDLDigital LogicHardwareALU

6-Bit ALU — Gate-Level VHDL & FPGA Implementation

Gate-level ALU with ripple-carry adder, two's complement subtraction, and Basys3 hardware testing.

Year: 2024Category: FPGA
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Project Overview

Designed and implemented a 6-bit ALU using only gate-level VHDL components, including ripple-carry adder, decoder logic, XOR/NOR operations, and full Basys3 hardware testing.

6-Bit ALU — Gate-Level VHDL & FPGA Implementation